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description the CXD2302Q is an 8-bit cmos a/d converter for video with synchronizing clamp function. the adoption of 2 step-parallel method achieves low power consumption and a maximum conversion rate of 50msps. features resolution: 8 bit 1/2lsb (dl) maximum sampling frequency: 50msps low power consumption: 125mw (at 50msps typ.) (reference current excluded) synchronizing clamp function clamp on/off function reference voltage self-bias circuit input cmos/ttl compatible 3-state ttl compatible output single 5v power supply or dual 5v/3.3v power supply low input capacitance: 15pf reference impedance: 370 ? (typ.) applications wide range of applications that require high-speed a/d conversion such as tv and vcr. structure silicon gate cmos ic absolute maximum ratings (ta = 25?) supply voltage v dd 7v reference voltage v rt ,v rb v dd + 0.5 to vss ?0.5v input voltage v in v dd + 0.5 to vss ?0.5v (analog) input voltage v i v dd + 0.5 to vss ?0.5v (digital) output voltage v o v dd + 0.5 to vss ?0.5v (digital) storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage av dd , avss 4.75 to 5.25 v dv dd , dvss 3.0 to 5.5 v | dvss ?avss | 0 to 100 mv reference input voltage v rb 0 and above v v rt 2.7 and below v analog input v in 1.7vp-p above clock pulse width t pw1 , t pw0 9ns (min) to 1.1s (max) operating ambient temperature topr ?0 to +85 ? ?1 CXD2302Q e94102f0z-ps 8-bit 50msps video a/d converter with clamp function sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 32 pin qfp (plastic)
?2 CXD2302Q block diagram 13 14 28 31 32 lower sampling comparator (4 bit) lower sampling comparator (4 bit) upper sampling comparator (4 bit) lower encoder (4 bit) lower encoder (4 bit) upper encoder (4 bit) lower data latch upper data latch clock generator 9 10 11 2 3 4 5 6 7 8 12 1 16 17 18 19 20 21 22 23 24 25 reference supply 15 26 27 29 30 vrbs vrb avss avss v in av dd av dd vrt vrts av dd oe dvss d 0 (lsb) d 1 d 2 d 3 d 4 d 5 d 6 d 7 (msb) test (open) nc dvss cle ccp v ref clp nc nc d-ff dv dd test (open) clk
3 CXD2302Q pin description pin no. symbol equivalent circuit description 1 to 8 9 10 11 12 13, 14, 32 d 0 to d 7 test dv dd test 15 clp 29 cle clk nc d 0 (lsb) to d 7 (msb) output leave open for normal use. digital power supply +5v or +3.3v leave open for normal use. pull-up resistor is built in. input the clamp pulse. clamps the signal voltage during low interval. pull-up resistor is built in. the clamp function is enabled when cle = low. the clamp function is set to off and the converter functions as a normal a/d converter when cle = high. pull-up resistor is built in. clock input. set to low level when no clock is input. 16, 19, 20 av dd analog power supply +5v dv dd dv ss di dv ss dv dd 9 av ss av dd 11 15 29 av ss av dd 12
4 CXD2302Q 17 vrts generates approximately +2.5v when shorted with av dd . 18 vrt 24 vrb reference voltage (top) reference voltage (bottom) av ss av dd 24 17 25 r t rref r b 18 21 v in analog input av ss av dd 21 26 vref clamp reference voltage input. clamps so that the reference voltage and the input signal during clamp interval are equal. av ss av dd 26 27 ccp integrates the clamp control voltage. the relationship between the changes in ccp voltage and in v in voltage is positive phase. av ss av dd 27 30 oe data is output when oe = low. pins d 0 to d 7 are at high impedance when oe = high. pull-down resistor is built in. av ss av dd 30 25 vrbs generates approximately +0.6v when shorted with av ss . 22, 23 av ss analog ground 28, 31 dv ss digital ground pin no. symbol equivalent circuit description
5 CXD2302Q t pw1 t pw0 n n + 1 n + 2 n + 3 n + 4 n + 1 n n 1 n 2 n 3 o: analog signal sampling point clock 1.3v analog input data output tp lh , tp hl 1.3v 0.7dv dd 0.3dv dd clock data output 90% 10% tr 4ns tf 4ns 3v 0v timing chart i -2. 3v tr = 4.5ns tf = 4.5ns 90% 10% 1.3v tp zl tp lz 1.3v tp zh tp hz 10% 90% 1.3v 0v v oh v ol ( dv ss ) v oh ( dv dd ) v ol output 2 output 1 oe input timing chart i -1. timing chart i -3. digital output the following table shows the relationship between analog input voltage and digital output code. input signal voltage step digital output code msb lsb v rt : : : : v rb 0 : 127 128 : 255 1 1 1 1 1 1 1 1 : 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 : 0 0 0 0 0 0 0 0 timing chart i
6 CXD2302Q electrical characteristics analog characteristics (fc = 50mhz, av dd = 5v, dv dd = 3 to 5.5v, v rb = 0.5v, v rt = 2.5v, ta = 25 c) item symbol conditions min. typ. max. unit max. conversion rate min. conversion rate analog input band width differential non-linearity error integral non-linearity error offset voltage ? 1 differential gain error differential phase error sampling delay clamp offset voltage ? 2 e oc snr fin = 100khz fin = 500khz fin = 1mhz fin = 3mhz fin = 10mhz fin = 25mhz fin = 100khz fin = 500khz fin = 1mhz fin = 3mhz fin = 10mhz fin = 25mhz 45 44 44 43 38 32 51 46 49 46 45 45 db db fsdr v in = dc c in = 10f t pcw = 2.75s fc = 14.3mhz fclp = 15.75khz v ref = 0.5v 02040 mv 02040 v ref = 2.5v signal-to-noise ratio spurious free dynamic range fc max. fc min. bw e d e l e ot e ob dg dp t sd 50 70 20 65 60 100 0.3 +0.7 50 40 3 1.5 0 0.5 0.5 1.5 30 60 msps mhz lsb mv % deg ns 1db 3db end point potential difference to vrt potential difference to vrb ntsc 40 ire mod ramp fc =14.3msps av dd = 4.75 to 5.25v ta = 40 to +85 c, v in = 0.5 to 2.5v f in = 1khz triangular wave envelope r in = 33 ? ? 1 the offset voltage eob is a potential difference between vrb and a point of position where the voltage drops equivalent to 1/2 lsb of the voltage when the output data changes from 00000000 to 00000001 . eot is a potential difference between vrt and a potential of point where the voltage rises equivalent to 1/2lsb of the voltage when the output data changes from 11111111 to 11111110 . ? 2 clamp offset voltage varies individually. when using with r, g, b 3 channels, color sliding may be generated.
7 CXD2302Q dc characteristics (fc = 50mhz, av dd = 5v, dv dd = 5v or 3.3v, v rb = 0.5v, v rt = 2.5v, ta = 25 c) supply analog current digital reference current reference resistance (v rt v rb ) self-bias voltage analog input resistance input capacitance output capacitance digital input voltage digital input current digital output current i ad + i dd i ad i dd i ref r ref v rb v rt v rb r in c ai1 c ai2 c din c ao c do v ih v il i ih i il i oh i ol i oh i ol i ozh i ozl 4.1 260 0.52 1.80 2.2 240 240 40 4 2.4 40 40 2 1.2 40 40 ma ma a 240 40 240 a 0.8 v 25 23 2 5.4 370 0.56 1.92 13 16 30 15 36 33 3 7.7 480 0.60 2.04 11 11 11 11 ma ma ? v k ? pf pf ntsc ramp wave input cle = 0v dv dd = 5v dv dd = 3.3v shorts v rts and av dd shorts v rbs and av ss vin fc = 50mhz fc = 35mhz fc = 20mhz vin, vin = 1.5v + 0.07vrms vrts, vrt, vrb, vrbs, vref test, clk, clp, cle, oe ccp d0 to d7, test av dd = 4.75 to 5.25v dv dd = 3 to 5.5v ta = 40 to +85 c v i = 0v to av dd ta = 40 to +85 c oe = 0v dv dd = 5v ta = 40 to +85 c oe = 3v dv dd = 3 to 5.5v ta = 40 to +85 c clk test, clp, cle oe v oh = dv dd 0.8v v ol = 0.4v v oh = dv dd 0.8v v ol = 0.4v v oh = dv dd v ol = 0v note) the voltage of up to (av dd + 0.5v) can be input when dv dd = 3.3v. but the output pin voltage is less than the dv dd voltage. when the digital output is in the high impedance mode, the ic may be damaged by applying the voltage which is more than the (dv dd + 0.5v) voltage to the digital output. oe = 0v dv dd = 3.3v ta = 40 to +85 c item symbol conditions min. typ. max. unit
8 CXD2302Q timing (fc = 50mhz, av dd = 5v, dv dd = 5v or 3.3v, v rb = 0.5v, v rt = 2.5v, ta = 25 c) output data delay tri-state output enable time tri-state output disable time clamp pulse width ? t p lh t p hl t p lh t p hl t p zh t p zl t p zh t p zl t p hz t p lz t p hz t p lz t cpw 9.5 8.5 11.8 7.6 4.5 6.0 7.0 5.0 5.5 5.5 2.75 ns ns ns s c l = 15pf oe = 0v r l = 1k ? c l = 15pf oe = 3v 0v r l = 1k ? c l = 15pf oe = 0v 3v fc = 14.3mhz, c in = 10f for ntsc wave dv dd = 5v dv dd = 3.3v dv dd = 5v dv dd = 3.3v dv dd = 5v dv dd = 3.3v 5.5 4.3 2.5 3.0 3.5 2.5 1.75 12.0 16.3 8.0 9.0 7.5 8.0 3.75 ? the clamp pulse width is for ntsc as an example. adjust the rate to the clamp pulse cycle (1/15.75khz for ntsc) for other processing systems to equal the values for ntsc. electrical characteristics measurement circuit output data delay measurement circuit tri-state output measurement circuit measurement point to output pin c l to output pin c l r l r l measurement point dv dd note) c l includes capacitance of probes. item symbol conditions min. typ. max. unit
9 CXD2302Q integral non-linearity error differential non-linearity error } test circuit offset voltage analog input resistance test circuit +v v a < b a > b comparator a8 to a1 a0 b8 to b1 b0 dut CXD2302Q buffer s1 s2 s1: on if a < b s2: on if b > a 8 8 controller dvm 8 000 00 to 111 10 clk (50mhz) v in "0" "1" differential gain error differential phase error } test circuit amp cxd 2302q ttl ecl 10bit d/a 5.2v 8 620 8 v in ntsc signal source vector scope d.g d.p. 5.2v 620 ttl ecl cx20202a-1 s.g. (cw) fc 40 ire modulation burst sync 2.5v 0.5v 100 0 40 iae clk digital output current test circuit v dd v rt v in v rb clk oe gnd 2.5v 0.5v v oh + i oh v dd v rt v in v rb clk oe gnd 2.5v 0.5v v ol + i ol d0 to d7 d0 to d7 +5v v rt v in v rb clk 0.5v 2.5v gnd v dd
10 CXD2302Q timing chart ii s (1) c (1) s (2) c (2) s (3) c (3) s (4) c (4) md (0) md (1) md (2) md (3) rv (0) rv (1) rv (2) rv (3) (1) (2) (3) (4) s (1) c (1) s (3) c (3) h (3) h (1) ld ( 1) ld (1) c (0) s (2) c (2) s (4) h (0) h (2) h (4) ld ( 2) ld (0) ld (2) out ( 2) out ( 1) out (0) out (1) vi (1) vi (2) vi (3) vi (4) external clock upper comparators block analog input upper data lower reference voltage lower comparators a block lower data a lower comparators b block lower data b digital output operation (see block diagram and timing chart ii ) 1. the CXD2302Q is a 2-step parallel system a/d converter featuring a 4-bit upper comparator block and 2 lower comparator blocks of 4-bit each. the reference voltage that is equal to the voltage between v rt v rb /16 is constantly applied to the upper 4-bit comparator block. voltage that corresponded to the upper data is fed through the reference supply to the lower 4-bit comparator block. vrts and vrbs pins serve for the self generation of v rt (reference voltage top) and v rb (reference voltage bottom), and they are also used as the sence pins as shown in the application circuit examples i -4 and i -5.
11 CXD2302Q 2. this ic uses an offset cancel type comparator which operates synchronously with an external clock. it features the following operating modes which are respectively indicated on the timing chart ii with s, h, c symbols. that is input sampling (auto zero) mode, input hold mode and comparison mode. 3. the operation of respective parts is as indicated in the timing chart ii . for instance input voltage vi (1) is sampled with the falling edge of the external clock (1) by means of the upper comparator block and the lower comparator a block. the upper comparator block finalizes comparison data md (1) with the rising edge of the external clock (2). simultaneously the reference supply generates the lower reference voltage rv (1) that corresponded to the upper results. the lower comparator a block finalizes comparison data ld (1) with the rising edge of the external clock (3). md (1) and ld (1) are combined and output as out (1) with the rising edge of the external clock (4). accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output. operation notes 1. v dd , v ss to reduce noise effects, separate the analog and digital systems close to the device. for both the digital and analog v dd pins, use a ceramic capacitor of about 0.1f set as close as possible to the pin to bypass to the respective gnd s. 2. analog input compared with the flash type a/d converter, the input capacitance of the analog input is rather small. however it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability. when driving with an amplifier of low output impedance, parasitic oscillation may occur. that may be prevented by insetting a resistance of about 33 ? in series between the amplifier output and a/d input. when the v in signal of pin no. 21 is monitored, the kickback noise of clock is. however, this has no effect on the characteristics of a/d conversion. 3. clock input the clock line wiring should be as short as possible also, to avoid any interference with other signals, separate it from other circuits. 4. reference input voltage v rt to v rb is compatible with the dynamic range of the analog input. bypassing v rt and v rb pins to gnd, by means of a capacitor about 0.1f, stable characteristics are obtained. by shorting v dd and v rts , v ss and v rbs respectively, the self-bias function that generates v rt =about 2.5v and v rb =about 0.6v, is activated. 5. timing analog input is sampled with the falling edge of clk and output as digital data synchronized with a delay of 2.5 clocks and with the following rising edge. the delay from the clock rising edge to the data output is about 9ns (dv dd = 5v). 6. oe pin pins 1 to 8 (d 0 to d 7 ) are in the output mode by leaving oe open or connecting it to dv ss , and they are in the high impedance mode by connecting it to dv dd .
12 CXD2302Q 10p 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 +5v (digital) 0.1 0.01 gnd (digital) gnd (analog) +5v (analog) +5v (analog) 0.01 d 7 clock in clamp pulse in video in 10 33 ? 0.1 v ref 20k 0.01 open aco4 d 6 d 5 d 4 d 3 d 2 d 1 d 0 25 10p 2 3 4 5 6 7 8 1 9 10 11 12 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +5v (digital) 0.1 gnd (digital) gnd (analog) +5v (analog) 0.01 clock in video in 10 33 ? 0.1 0.01 open aco4 subtracter comparator etc. clamp level setting data dac pwm etc. information other than that for clamp interval is at high impedance. 13 ? the relationship between the changes in ccp voltage (pin 27) and in v in voltage is positive phase. ? ? vin/ ? vccp = 3.0 (fs = 20msps) i -2. digital clamp (self-bias used) application circuit i. single +5v power supply i -1. when clamp is used (self-bias used)
13 CXD2302Q 10p gnd (analog) 2 3 4 5 6 7 8 1 9 10 11 12 13 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +5v (digital) 0.1 gnd (digital) +5v (analog) 0.01 clock in video in 33 ? 0.1 0.01 open aco4 14 15 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 i -3. when clamp is not used (self-bias used) +5v (analog) gnd (analog) 10p 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 +5v (digital) 0.1 0.01 gnd (digital) +5v (analog) 0.01 clock in clamp pulse in video in 10 33 ? 0.1 v ref 20k 0.01 open aco4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 25 vrb vrt i -4. when clamp is used (self-bias not used)
14 CXD2302Q ii . dual +5v/+3.3v power supply ii -1. when clamp is used (self-bias used) gnd (analog) 10p 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 +3.3v (digital) 0.1 0.01 gnd (digital) +5v (analog) +5v (analog) 0.01 clock in clamp pulse in video in 10 33 ? 0.1 v ref 20k 0.01 open aco4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 +5v (analog) gnd (analog) 10p 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26 27 28 29 30 31 32 +5v (digital) 0.1 gnd (digital) 0.01 clock in video in 33 ? 0.1 0.01 open aco4 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 25 vrb vrt i -5. when clamp is not used (self-bias not used)
15 CXD2302Q example of representative characteristics ambient temperature vs. supply current ambient temperature [ c] 20 0 25 50 75 24 25 26 supply current [ma] fc = 50mhz ntsc ramp wave input av dd = dv dd = 5v supply voltage vs. supply current supply voltage [v] 4.75 5 5.25 23 25 27 supply current [ma] fc = 50mhz ntsc ramp wave input av dd = dv dd ta = 25 c sampling frequency vs. supply current sampling frequency [msps] 10 30 40 50 15 20 25 supply current [ma] ntsc ramp wave input av dd = dv dd = 5v ta = 25 c 20 ambient temperature vs. maximum operating frequency ambient temperature [ c] 20 25 50 75 60 65 70 maximum operating rate [msps] fc = 50mhz fin = 1khz, triangular wave input av dd = dv dd = 5v 0 ambient temperature vs. sampling delay ambient temperature [ c] 20 25 50 75 1 0 1 sampling delay [ns] fc = 50mhz av dd = dv dd = 5v 0 input frequency vs. supply current input frequency [mhz] 0.01 1 10 25 25 30 35 supply current [ma] fc = 50mhz sine wave 1.9vp-p av dd = dv dd = 5v ta = 25 c 0.1 supply voltage vs. maximum operating frequency supply voltage [v] 4.75 5 5.25 63 65 67 maximum operating rate [msps] fc = 50mhz ntsc ramp wave input av dd = dv dd analog input band analog input frequency [mhz] 0.1 10 100 3 0 1 output level [db] fc = 50mhz sine wave 1vp-p input av dd = dv dd = 5v ta = 25 c 1
16 CXD2302Q analog input frequency vs. snr, effective bit analog input frequency [mhz] 0.01 0.1 1 10 30 40 50 snr [db] fc = 50mhz av dd = dv dd = 5v v in = 2vp-p ta = 25 c 8 7 6 5 effective bit [bit] ambient temperature vs. output data delay ambient temperature [ c] 20 25 50 75 6 10 12 output data delay [ns] fc = 10mhz av dd = dv dd = 5v c l = 15pf 0 8 tp lh tp hl load capacitance vs. output data delay load capacitance [pf] 5152025 8 10 12 output data delay [ns] fc = 10mhz av dd = dv dd = 5v ta = 25 c 10 6 0 tp hl tp lh dv dd supply voltage vs. output data delay dv dd supply voltage [v] 34.555.5 8 10 12 output data delay [ns] fc = 10mhz av dd = 5v c l = 15pf ta = 25 c 3.5 6 tp lh tp hl load capacitance vs. output data delay load capacitance [pf] 51525 8 10 12 output data delay [ns] fc = 10mhz av dd = 5v dv dd = 3.3v ta = 25 c 6 14 0 10 20 tp lh tp hl ambient temperature vs. output data delay ambient temperature [ c] 20 25 50 75 8 10 12 output data delay [ns] fc = 10mhz av dd = 5v dv dd = 3.3v c l = 15pf 0 6 tp lh tp hl analog input frequency vs. fsdr analog input frequency [mhz] 0.01 1 10 40 50 60 fsdr [db] fc = 50mhz av dd = dv dd = 5v v in = 2vp-p ta = 25 c 0.1 30 0.5 1.5 2.5 80 0 80 analog input voltage vs. input current analog input voltage v in [v] analog input current i ai [a] fc = 50mhz av dd = dv dd = 5v v rt = 2.5v v rb = 0.5v ta = 25 c
17 CXD2302Q 8-bit 50msps adc and dac evaluation board evaluation boards are available for the high speed, low power consumption cmos converters CXD2302Q (8-bit 50mhz a/d) and cxd1171m (8-bit 40mhz d/a). the evaluation boards are composed of a main board, CXD2302Q sub board and cxd1171m sub board. the each board is connected with sockets. an input interface, clock buffer and latches are mounted on the main board. the CXD2302Q and cxd1171m are mounted on each of the sub boards. those ics are mounted according to recommended print patterns designed to provide maximum performance to the a/d and d/a converters. block diagram analog circuit mount portion analog input interface analog circuit mount portion v ref adc socket dac socket clock buffer data latch osc digital circuit mount portion 5v +5v gnd clock oe sel sync cle blk v out v in sw 8 8 4 unnecessary at self bias use characteristics resolution 8bit maximum conversion rate 50mhz digital input level cmos level supply voltage 5.0v (single +5v power supply possible at self bias use) supply voltage item +5v 5v 185 20 ma min. typ. max. unit clock input cmos compatible pulse width t cw1 10ns (min) t cw0 10ns (min)
18 CXD2302Q analog output (cxd1171m) (r l > 10k ? ) item analog output 1.8 2.0 2.1 v min. typ. max. unit output format (CXD2302Q) the table shows the output format of ad converter. analog input voltage v rt : : : : v rb 0 : 127 128 : 255 11111111 : 10000000 01111111 : 00000000 step digital output code msb lsb analog input external clock ad clock ad output latch output da input da clock da output t pd (da) ts th t dd tdc tpw 1 tpw 0 t pd (ad) timing chart item clock high time clock low time clock delay data delay ad data delay (latch) settling time hold time data delay da t pw1 t pw0 tdc t pd (ad) t dd t s t h t pd (da) 10 10 5 10 symbol min. 9 10 typ. 24 17 max. ns ns ns ns ns ns ns ns unit
19 CXD2302Q nc nc av ss av ss iref vref av dd av dd io io nc dv dd nc dv ss clk blk d7 d6 d5 d4 d3 d2 d1 d0 clk dv dd d7 d6 d5 d4 d3 d2 d1 d0 dv ss oe clp nc nc v rt av dd av dd v in av ss av ss v rb v ref cle r8 3.3k (16r) r7 200 (r) v out vr4 20k output gain adjust 13 14 15 16 17 18 19 20 21 22 23 24 q2 r5 510 vr2 2k av dd vrt adjust q1 vr1 2k r6 510 r4 510 vrb adjust sw1 sw2 c3 0.01 c4 0.01 sw3 vr3 20k av dd r3 33 c2 10 r2 75 av ss q3 c1 470 r1 100k video input clamp voltage adjust 47 av ss 5v +5v gnd av dd dv dd 74s174 (latch) dv dd 0.01 0.01 0.01 13 14 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12 1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 dv dd clk dv dd clk dv ss clear dv ss clear dv ss 2 3 4 5 6 7 1 8 9 10 11 12 13 14 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 9 10 11 12 13 14 15 16 74s174 (latch) 74s04 or 74hc04 (inv buffer) c5 0.1 osc switch ext/int blk sync oe sel cle r9 75 r10 75 47 8 7 1 dv ss 14 0.01 dv dd external clock input sync int (r in = 75 ? ) 0.01 dv dd dv ss dv dd dv ss osc out vr5 20k cmos adc/dac peripheral circuit board (main board)
20 CXD2302Q cmos adc/dac peripheral circuit board (sub board) clp nc nc v rt av dd av dd v in av ss av ss v rb v ref cle CXD2302Q clk dv dd d7 d6 d5 d4 d3 d2 d1 d0 dv ss oe 9 10 11 12 13 14 15 16 2 3 4 5 6 7 8 1 9 10 11 12 13 14 2 3 4 5 6 7 8 1 c3 0.1 c5 c4 c2 0.1 25 26 27 28 29 30 31 32 c1 0.01 17 18 19 20 21 22 23 24 15 16 25 26 27 28 17 18 19 20 21 22 23 24 jt jb nc nc av ss av ss i ref v ref av dd av dd io io nc dv dd cxd1171m dv ss clk blk d7 d6 d5 d4 d3 d2 d1 d0 nc c1 c4 9 10 11 12 2 3 4 5 6 7 8 1 c2 c3 13 14 15 16 17 18 19 20 21 22 23 24 9 10 11 12 2 3 4 5 6 7 8 1 13 14 17 18 19 20 21 22 23 24 15 16
21 CXD2302Q list of parts resistance r1 100k r2 75 ? r3 75 ? r4 510 ? r5 510 ? r6 510 ? r7 r = 200 r8 18r 3.3k r9 75 ? r10 75 ? vr1 2k vr2 2k vr3 20k vr4 20k vr5 20k capacitance c1 470f/6.3v (chemical) c2 10f/16v (chemical) c3 0.01f c4 0.01f c5 0.1f c6 0.1f c7 0.1f c8 0.1f c9 0.1f c10 0.1f c11 47f/10v (chemical) c12 47f/10v (chemical) c13 47f/10v (chemical) c14 0.1f transistor q1 2sc2785 q2 2sc2785 q3 2sc2785 ic ic1 74s174 ic2 74s174 ic3 74s04 oscillator osc others connector bnc071 sw at1d2m3 adjustment 1. vref adjustment (vr1, vr2) adjustment of a/d converter reference voltage. vrb is adjusted through vr1 and vrt through vr2. when self bias is used, there is no need for adjustment. reference voltage is set through self bias delivery. 2. setting of clamp reference voltage (vr3) clamp reference voltage is set. 3. dac output full scale adjustment (vr4) full scale voltage of d/a converter output is adjusted at the pcb shipment, the full scale voltage is adjusted to approx. 2v. 4. sync (clamp) pulse interface (vr5) this adjustment enables interface with the signal generator and others at the pcb shipment, adjustment is performed to obtain a threshold of approx. 2.5v to an h sync of 0 to 5v.
22 CXD2302Q 5. oe, sel, sync, blk, cle, sync int the following pins are set on the main board: oe, sync, cle, sync int (CXD2302Q), blk (cxd1171m) and sel (not used). for the pins function, refer to the pin description. the difference between sync pin and sync int pin is that a pulse above 3.5vp-p should be input to sync int pin. the pulse threshold is set through vr5. for input through sync pin, pulse is input at ttl or cmos level. in this case cut off the junction line between sync and sync int pin. at the pcb shipment the main board pins are set as follows. oe : low (a/d output on) sel : low sync : line junction sync int pin cle : low (clamp function on) blk : low (blanking off) 6. clamp pulse input method directly input the clamp pulse as shown in application circuit example i -1. as sw1 is set to direct input at the pcb shipment, use it in this position. points on the pcb pattern layout 1. set the layout not to have digital current flow into analog gnd (for 1, see p.24 component side diagram .). 2. the c 2 and c 3 capacitors for the CXD2302Q sub board serve the important role of bringing out ics full performance. connect over 0.1f (ceramic) capacitors with good high frequency characteristics as close to the ic as possible. 3. analog gnd (av ss ) and digital gnd (dv ss ) are on a common voltage supply source. keeping adc s dv ss (for 2, see p.24 component side diagram .) as close to the voltage supply source as possible will provide better characteristics. that is, a layout where adc is close to the voltage supply source, is recommended. 4. adc samples analog signals at the clock falling edge. accordingly it is important that clocks supplied to adc do not have any jitter. 5. the pcb layout shows adc and dac s analog gnd independently from the voltage supply source. the layout aims at providing an independent evaluation of adc and dac, as much as possible. on the actual board, common use will not cause any problems.
23 CXD2302Q notes on operation 1. reference voltage shorting av dd and v rts , av ss and v rbs will activate the self-bias function that generates v rt = about 2.6v and v rb =about 0.5v. on the pcb, either self bias or the external reference voltage can be selected depending on the junction method of the jumper line. at shipment from the factory, reference voltage is provided in self bias. also, to provide external reference voltage, adjust the dynamic range (v rt v rb ) to above 1.8vp-p. 2. clock input there are 2 modes for the pcb clock input 1) provided from the external signal generator. (external clock) 2) using the crystal oscillator (built-in clock driver). (internal clock) the 2 modes are selected using the switch on the pcb. 3. the 2 latch ics (74s174) are not absolutely necessary for the evaluation of adc and dac. that is, operation will still be normal if adc output data is directly input to dac input. however, as adc output data is hardly ever d/a converted without executing digital signal processing, it was mounted to indicate an example layout of digital signal processing ic. use the latch ic output when the adc output data is used. 4. when clamp is not used turning cle to h will set off the clamp function. in this case, the dc element is cut off by means of c 2 on the main board and dc voltage on the adc side of c 2 turns to about (v rt +v rb )/2. to transfer dc elements of input signals, short c 2 . at that time, it is necessary to bias input signals, but keeping r 2 open, q 3 can also be used as buffer. use the open space for the bias circuit. 5. clamp pulse latch on the evaluation board, the clamp pulse is latched with adc sampling clk and then input to clp pin. however, the latch is incorporated in clp pin of the CXD2302Q, so that the external latch is not required. 6. peripheral through hole there is a group of through holes on the analog input, output and logic. there are to be used when mounting additional circuits to the pcb. use when necessary. the connector hole on dac part is used to mount the test chassis mount jack.
24 CXD2302Q component side soldering side (diagram seen from the component side) silk side
25 CXD2302Q package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder plating 42 / copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 ?0.1 1.5 ?0.15 (8.0) 0.1 ?0.1 + 0.2 + 0.35 + 0.3 0.50 0? to 10? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 ?0.10 ( 0.30) (0.127) + 0.15 detail a : solder a 0.127 ?0.05 + 0.10
26 CXD2302Q sony corporation package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin palladium plating copper alloy 32pin qfp (plastic) 9.0 0.2 7.0 0.1 1.5 0.15 (8.0) 0.1 0.1 + 0.2 + 0.35 + 0.3 0.50 0 ? to 10 ? 0.8 b 1 8 9 32 16 17 24 25 m 0.24 0.2g qfp-32p-l01 p-qfp32-7x7-0.8 0.1 b = 0.30 0.03 0.125 0.04 detail a : palladium a

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